1. Field of the Invention
This invention relates to a semiconductor integrated circuit device for storing a flash memory and also relates to a memory control method for regulating access to that flash memory.
2. Description of Related Art
Demand has been increasing in recent years for EEPROM emulations to add a small data capacity to the flash memory as a substitute for an external EEPROM. These EEPROM applications require an extremely large number of rewrite operations and so must provide reliability for this (large) number of rewrites.
In the technology disclosed in Japanese Patent Laid Open Application No. 2006-48893, the hardware selects a spare block address as the physical address from the defect block mapping information and the control address that was received. The flash memory includes a memory cell array unit, a defect block mapping register unit, an address selector unit, and a defect block status control unit. The memory cell array unit stores the data by way of the received physical address, and stores the defect block mapping information. The defect block mapping register unit stores the defect block mapping information. The address selector unit generates a defect block address by selecting a spare block address matching the logical address or an externally applied logical address, as the physical address. The defect block control status unit receives the defect block address from the address selector unit, and updates the defect block mapping information in the defect block mapping register. The defect block status control unit counts the number of defect block addresses stored in the defect block mapping register unit, and controls the selection operation performed by the address selector unit. The defect block status control unit then stores the defect block mapping information stored in the defect block mapping register unit, into the memory cell array unit.
In other words, the defect block information read out (loaded) from the mapping information storage block in the flash memory is stored in the defect block mapping register unit. The address selector unit compares the logical address that was received externally, with the defect block mapping table. If this comparison results in access to a defect block, then a spare block address is output to the memory cell array.
The flash memory cell contains multiple memory cells each connected to one word line and bit line. In the case of a flash memory, the bit lines are often jointly shared by all blocks so if a defect such as a locked state occurs on a specific bit line then that defect is a defect on all blocks.
If a breakdown occurs on the word lines/bit lines of the memory cell, then that affects the entire memory so merely replacing the block will not cure the defect.